Homework 11: Reliability and Safety Analysis Team Code Name



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ECE 477 Digital Systems Senior Design Project Rev 9/12

Homework 11: Reliability and Safety Analysis


Team Code Name: _Mind Readers________________________________ Group No. _2____

Team Member Completing This Homework: _Matt Waldersen_________________________

E-mail Address of Team Member: _mwalders_____ @ purdue.edu

Evaluation:

SEC

DESCRIPTION

MAX

SCORE


1.0

Introduction

5

4


2.0

Reliability Analysis

40

40


3.0

Failure Mode, Effects, and Criticality Analysis (FMECA)

40

35


4.0

Summary

5

5


5.0

List of References

10

8




TOTAL

100

92



Comments:

Grader: George Toh
Great job. There were more FEMCA failure modes that could have been considered, but you did a good job with those listed. Order your references correctly in the future (using the MSWord references manager)

  1. Introduction

The Mind Reader is a mobile brain computer interface system that uses electrooculography (EOG) and electroencephalogram (EEG) signals to navigate a heads mounted display. In any system that requires on biological signals, reliability and safety is of the upmost importance. The most critical reliability and safety issues faced by the Mind Reader are the complex components used in the Mind Reader Design and their high power consumption.


  1. Reliability Analysis


The three components included in the Mind Reader’s design that are most likely

to fail and are not part of a premade commercially available device (i.e. the Beagleboard-xm Single-Board Computer [5], the NeuroSky Mindwave EEG [8], the Vuzix Wrap 920 Eyewear [7]) are the Microchip dsPIC33EP512MU810 microcontroller [2], the Linear Technology LT1374 step-down switching regulator [4] and the Texas Instruments ADS1210 analog-to-digital converter module [3]. The dsPIC33EP512MU810 microcontroller is likely to fail due to its high level of complexity, the LT1374 step-down switching regulator is likely to fail due to its high level of power consumption and the ADS1210 analog-to-digital converter was chosen as a likely candidate to fail due to its high level of complexity.


    1. Microcontroller




Model:

Monolithic Bipolar and MOS Digital Microprocessor Devices

λP Calculation

λP = (C1πT + C2πE)πQπL




Parameter

Description

Value

Comments

C1

Die Complexity Constant

0.2800

16-Bit Microcontroller

πT

Temperature Coefficient

0.4500


TJ = TC + PDθJC

TC = 50 °C

θJC = 10 °C/W

PD = PINT + PI/O

PINT = VDD(IDD – ΣIOH) = 0.996 W

PI/O = Σ([VDD – VOH][IOH]) + Σ(VOL x IOL)

PI/O = 0.2145

PD = 0.966 + 0.2145 = 1.2105

TJ = 62.105 °C

Assumed worst case values for IDD, IOH and IOL


C2

Pin Number Constant

0.0520

NP = 100; Non-Hermetic Seal

πE

Environmental Constant

4.0000

Mobile Ground Environment

πQ

Quality Factor

1.0000

Class B Safety Qualification

πL

Learning Factor

0.7300

Greater than 2 years in production

λP

0.2443 failures per 106 hours

MTTF

467.2938 years per failures


The model used for the microcontroller was “Monolithic Bipolar and MOS Digital Microprocessor Devices”. The one major assumption made was to assume the maximum values for IDD, IOH and IOL. This assumption was made to account for the fact that these values can vary with different computational loads and power dissipation. For a microcontroller as complex as the dsPIC33EP512MU810 it is fairly reliable, with that said there are several design changes that could be made to increase the system’s reliability. The first way would to be to select a microcontroller that operates on 5V logic as opposed to 3.3V logic. This would eliminate the need for multiple logic level translators and switch mode power supplies. The second way would be to select a form factor with fewer pins. A majority of the pins are unused, which ultimately results in an unnecessarily high value of C2.



    1. Step-Down Switching Regulator




Model:

Transistor, Low Frequency, SI FET

λP Calculation

λP = λbπTπAπQπE




Parameter

Description

Value

Comments

λb

Base Failure Rate

0.0120

Modeled as a Power MOSFET

πT

Temperature Factor

4.4982


TJ = TC + PDθJC

TC = 50 °C

θJC = 80 °C/W

PD = 0.4227 W

TJ = 115.4139 °C


πA

Application Factor

4.0000

Pr = (4.5A)(5V)

πQ

Quality Factor

5.5000

Assumed Lower Quality

πE

Environmental Factor

9.0000

Ground Mobile Environment

λP

10.68 failures per 106 hours

MTTF

10.69 years per failures


The Transistor, Low Frequency, SI FET model used for the LT1374 due to its similar functionality to a power MOSFET. The one major assumption made was that the quality factor was of lower quality. This assumption was made in order to make the MTTF calculations as conservative as possible. The LT1374 has a very low MTTF value mostly because of the temperature factor. A way to make the Mind Reader’s design more reliable would be to utilize a more temperature efficient form factor of the LT1374. Form factors that utilize a thermal dissipation pad would lower the temperature factor and result in a more reliable system without having to sacrifice functionality.


    1. Analog-to-Digital Converter




Model:

Monolithic Bipolar and MOS Digital Microprocessor Devices

λP Calculation

λP = (C1πT + C2πE)πQπL




Parameter

Description

Value

Comments

C1

Die Complexity Constant

0.2800

Assumed 32-Bit Microcontroller

πT

Temperature Coefficient

0.2900


TJ = TC + PDθJC

TC = 50 °C

θJC = 10 °C/W

PD = 0.026 W

TJ = 50.26°C



C2

Pin Number Constant

0.0064

NP = 18; Hermetic Seal

πE

Environmental Constant

4.0000

Ground Mobile Environment

πQ

Quality Factor

10.0000

Other Commercial or Unknown Screening Levels

πL

Learning Factor

0.0078

Greater than 2 years in production

λP

0.0083 failures per 106 hours

MTTF

13703.4538 years per failures


The model used for the ADS1210 was the “Monolithic Bipolar and MOS Digital Microprocessor Devices” due to the fact it includes a microcontroller in its design. It was assumed that the microcontroller utilized a 32-bit architecture due to the size of its command register. The system could be designed to be more reliable if an external reference input was used. If the reference output is disabled and an external source is used to program the reference input, the power dissipation decreases by ~33%. A graph of this difference in power dissipation is shown on page 8 of the ADS1210 data sheet. This drop in power dissipation would decrease the temperature coefficient, which would result in an increase in system reliability.


  1. Failure Mode, Effects, and Criticality Analysis (FMECA)


High Criticality: A failure of a high level of criticality is defined as a failure that would result in injury to the user. The rationale behind this definition is that a system failure that results in the harm of its user should not be allowed to happen. Failures of high criticality must have a λ < 10-9.
Medium Criticality: A failure of a medium level of criticality is defined as a failure that results in that the Mind Reader no longer has the ability to:


  • Encode/Decode Data Packets from a NeuroSky EEG.

  • Allow the user to select applications based on signals from a NeuroSky EEG.

  • Allow the user to navigate between different applications on a display using EOG signals.

  • Interactively train the user to effectively operate the device.

  • Overlay applications onto a live video stream.


The rationale behind this definition is that failures that prevent the device from performing its most fundamental functionality should be considered more severe than failures that don’t entirely prevent the device from functioning. Failures of medium criticality must have a λ < 10-7.
Low Criticality: A failure of a low level of criticality is defined as a failure that results in non-ideal operation of the device that does not result in a loss of major functionality and does not harm the user. Failures of low criticality must have a λ < 10-6. The rationale behind this definition is that failures that don’t result in harm of the user or loss of core functionality are considered to be of the lowest priority and severity.
The schematic has been divided into 3 functional blocks that are the microcontroller schematic, the EOG schematic and the power supply circuitry. A major assumption made while completing the FEMCA worksheets were that it is assumed that all pre-manufactured subsystems (the single board computer, the FPGA module, lithium ion protection circuitry and the NeuroSky EEG) have been pretested and will not fail. The reason for this is because there is nothing the Mind Readers team can do to redesign the reliability of these systems other than selecting eliminating it from the design. Other assumptions made include that all components are installed correctly, failures don’t result from environmental conditions and that only one functional block is failing at a time. Examples of how environmental conditions could result in failure would be if the EOG electrodes were directly connected to a power supply creating a short across the user’s face. Though a failure of this nature is possible, it would not occur as a result of component failure. The reason it is assumed that all other functional blocks are functioning properly is to eliminate failure mode redundancy. It is also assumed that there are no failures resulting from software failures.
Failure P1 was given a high criticality level due to the fact that if the single board computer loses power the user view is temporarily blocked. Depending on the situation, this could result in serious injury to the user. Possible ways to eliminate this possibility would be to include video glasses with transparent displays in the future.
Failure P5 was given a low criticality level due to the fact it doesn’t entirely eliminate EOG functionality. Unlike P4, only the analog circuitry requires -5V and only half of the raw EOG signal is of negative voltage. This would severely limit the device functionality, but is still considered low criticality because it doesn’t completely eliminate EOG functionality.


  1. Summary


This report outlines several reliability and safety issues faced the Mind Reader faces. Some of the most unreliable components in the Mind Reader design are the microcontroller, the analog-to-digital converter module and the switch mode power supply that powers the single board computer. The microcontroller and analog-to-digital converter module are likely to fail due to their high level of complexity and the switch mode power supply is likely to fail due to the high levels of power it is required to supply.
5.0 List of References


  1. Military Handbook Reliability Prediction of Electronic Equipment, MIL-HDBK-217F, The United States of America Department of Defense, Washington DC, 1991




  1. Microchip Technology, “dsPIC33EPXXX(GP/MC/MU)”, November 2011. [Online]. Available: http://www.digikey.com/product-detail/en/DSPIC33EP512MU810-I%2FPT/DSPIC33EP512MU810-I%2FPT-ND/2712350




  1. Texas Instruments, “ADS1210”, September 2005. [Online] Available: http://www.ti.com/lit/ds/symlink/ads1210.pdf




  1. Linear Technology, “LT1374”, 1998. [Online] Available: http://cds.linear.com/docs/Datasheet/1374fd.pdf




  1. BeagleBoard, “BeagleBoard-xM Rev-C System Reference Manual”, April 4, 2012. [Online]. Available: http://beagleboard.org/hardware-xm




  1. DLP Design, “USB – FPGA Module”, April 2012. [Online]. Available: http://www.dlpdesign.com/fpga/hsfpga3.shtml




  1. Vuzix, “WrapTM 920 Video Eyewear” 2009. [Online] Available: http://www.vuzix.com/site/_photo/sheet/Wrap_920_Product_Sheet_329PB0005_A.pdf




  1. NeuroSky, “Mindwave EEG”, 2012. [Online]. Available: http://neurosky.com/Products/MindWave.aspx


Appendix A: Schematic Functional Blocks


Figure A.1.1: EOG Digital Circuitry
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