Asian ibis summit information 亚洲ibis技术研讨会 Time/Date



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ASIAN IBIS SUMMIT INFORMATION

亚洲IBIS技术研讨会

Time/Date: 8:00 - 17:30, Tuesday, December 6, 2005

2005年12月6日,星期二,8:00 - 17:30


Location: Crowne Plaza Hotel Shenzhen 深圳威尼斯大酒店

9026 Shennan Rd, OCT 深南路9026号

Shenzhen, 518053 深圳,518053

P R CHINA 中华人民共和国

Tel: 86-755-26936888 电话:86-755-26936888

Fax: 86-755-26936999 传真:86-755-26936999

E-mail: cpsz@cpsz.com E-mail: cpsz@cpsz.com

http://www.ichotelsgroup.com/h/d/cp/1/en/hd/SZXNS
Room: Crowne Plaza Ballroom #2, First Floor

1楼威尼斯2号宴会厅


Registration: FREE, 免费
Sponsors: Huawei Technologies (Primary)

Cadence Design Systems, Mentor Graphics Corporation,

Signal Integrity Software (SiSoft) and Sigrity

IBIS SUMMIT MEETING AGENDA

IBIS技术研讨会日程表

8:15 REFRESHMENTS & SIGN IN 签到,点心

- Vendor Tables Open

9:00 Introductions and Program Overview 与会者和会议介绍

- Welcome, Jiang, XiangZhong, (Huawei Technologies, China)

- Welcome to Summit, Mirmak, Michael (Intel Corporation, USA)

- Welcoming Comments, Invited Chinese Leader/Speaker (China)

9:30 IBIS and Behavioral Modeling

- Mirmak, Michael (Intel Corporation, USA)
9:45 Fiberhome Telecommunications Technology Experiences with IBIS Models

- Zheng, Qi (Fiberhome Telecommunications Technology, China)


10:15 BREAK (Refreshments) 休息,点心
10:30 Simulation with IBIS in Tight Timing Budget Systems

- Sui, ShiJu, (ZTE Corporation, China)


11:00 Three Facets of IBIS: Interface, Behavior and Measurement

- Dodd, Ian* and Li, Henry** (Mentor Graphics Corporation, *USA and **China)


11:30 JEITA EDA - WG Activity and Study of Interconnect Model

- Watanabe, Takeshi (NEC Electronics Corporation, Japan)


12:00 FREE BUFFET LUNCH (Hosted by Sponsors) 自助午餐

- Vendor Tables


12:00 - 12:45 Press Conference for IBIS Officers and Sponsor 新闻发布会
13:30 IBIS and Power Delivery Systems

- Jiang, XiangZhong, Li, JinJun, and Zhang, ShengLi (Huawei Technologies, China)


14:00 Power Delivery System, Signal Return Path and SSO Analysis Guidelines

- Chen, Raymond Y. and Chitwood, Sam (Sigrity, USA)


14:30 Splitting the C_comp for Power Integrity Simulations

- Yang, Zhiping (Apple Computer, USA)


15:00 Using IBIS for SI Analysis

- Wang, Lance* and Zhong, ZhangMin** (Cadence Design Systems,

*USA and **China)
15:30 BREAK (Refreshments) 休息,点心
15:45 Macro Model and Multi-GHz System Simulation

- Zhu, ShunLin (ZTE Corporation, China)


16:15 IBIS Models for DDR2 Analysis

- Katz, Barry (Signal Integrity Software (SiSoft), USA)


16:40 Practical Measurement vs. Simulation Correlation with DDR2 667 Interface

- Shoji, Kazuyoshi (Hitachi ULSI Systems Co., Japan)


17:05 Improving IBIS ECL Algorithms

- Ross, Bob (Teraspeed Consulting Group, USA)


17:20 Concluding Items 会议闭幕

17:30 END OF IBIS SUMMIT MEETING 结束



- Final Vendor Tables and Teardown


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